Galaxy s7 edge crash

[[Unknown]]

No, thank you for testing. The hard part is really the trial and error in situations like this - we don't really know what's going on, so we have to probe the situation to figure out.

The test with block link on and the aligned code blocks sounds super good, but it's also super wasteful. Some games will hit performance problems because the jit cache space is being wasted so fast (games that run a lot of code every frame.)

Block linking is a good thing, but it's an optimization that only *sometimes* (well, most of the time) kicks in. I'm worried that if it crashes with it off, other games (or areas of this game) might crash even with it on. Even so, it's definitely major progress. We don't test with it off much, so I'm hoping there's just a bug happening when block cache is off.

If we can decrease the alignment a bit, it would really save space. Can you try this version?

Code:

while (((intptr_t)GetCodePtr()) & 0x3F) {
        HINT(HINT_NOP);
    }

(0xFF -> 0x3F)

If that works, we can try 0x1F or 0x0F too, which would waste even less space. My guess is that 0x3F is the lowest we can go, because that's the typical size of a cache line.

Another idea, that would be even better, is to disable that, and change the original code (from the post with instructions) to this:

Code:

void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end)
{
    start = m_startcode + 4096 < start ? start - 4096 : m_startcode;
    end += 4096;
    while ((intptr_t)start & 0xFC) {
        start -= 4;
    }
    while ((intptr_t)end & 0xFC) {
        start += 4;
    }
#if defined(IOS)
    // Header file says this is equivalent to: sys_icache_invalidate(start, end - start);
    sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
#else
#if defined(__clang__) && !defined(_M_IX86) && !defined(_M_X64)
    __clear_cache(start, end);
#else
#if !defined(_M_IX86) && !defined(_M_X64)
    __builtin___clear_cache(start, end);
#endif
#endif
#endif
}

This is a quick hack, but it aligns the start and end addresses of cache clears to 256. If aligning the cache clears is all that's needed, we don't need to waste space with the jit blocks. It'd be great if this option worked.

If it does, even better would be to reduce the three 4096s to like 256 or 64, or even 0. If it works with aligned clears with 0 padding, that would be awesome. There'd probably be nearly no performance penalty (some of this penalty is not immediately obvious... e.g. might cost more during loading than during actual gameplay, but both matter.)

All of this with block linking on.

Thanks again for the testing.

-[Unknown]